Memory device, memory device test method, and test system
US12300344B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2023 |
| Grant date | May 13, 2025 |
| Priority date | — |
| Expiry date | Sep 15, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/12015
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device according to an embodiment includes a memory cell array; a timing circuit configured to generate a first clock signal and a second clock signal, the second clock signal having a frequency that is i-times the frequency of the first clock signal; a command decoder configured to receive On-The-Fly (OTF) data including a plurality of OTF bits; a receiver configured to receive input data, sample the input data based on the first clock signal, and generate a first signal based on the sampled input data; a deserializer configured to generate a first deserialized signal from the first signal based on the second clock signal; a data pattern generator configured to generate a pattern signal based on the first deserialized signal and the OTF data based on the second clock signal; and a decoder configured to transmit the pattern signal to the memory cell array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.