Receiving circuit and memory
US12300350B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 6, 2023 |
| Grant date | May 13, 2025 |
| Priority date | — |
| Expiry date | Jun 7, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A receiving circuit includes: an input buffer configured to receive a first input signal and a second input signal, compare the first input signal with the second input signal, and output a first output signal and a second output signal, where the first input signal and the second input signal are respectively a first signal and a second signal in a differential mode, the first input signal is one of the first signal and the second signal in a single-ended mode, the second input signal is a reference voltage signal, and the first signal and the second signal are complementary; and a conversion module configured to receive the first output signal and the second output signal and amplify a voltage difference between the first output signal and the second output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.