Wordline driver circuit and memory
US12300354B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 22, 2022 |
| Grant date | May 13, 2025 |
| Priority date | — |
| Expiry date | Aug 2, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments relate to the field of semiconductors and provide a wordline driver circuit and a memory. The wordline driver circuit may at least include a plurality of wordline drivers. Each of the plurality of wordline drivers includes a corresponding PMOS transistor and an NMOS transistor, the plurality of PMOS transistors included in the plurality of wordline drivers are arranged side by side, and the plurality of NMOS transistors included in the plurality of wordline drivers are arranged side by side. In an arrangement direction of the plurality of PMOS transistors, the plurality of PMOS transistors are positioned on the same sides of the plurality of NMOS transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.