Wafer placement table
US12300476B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2022 |
| Grant date | May 13, 2025 |
| Priority date | — |
| Expiry date | Jun 7, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J2237/2007
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer placement table includes a ceramic base, an electrode (FR attraction electrode), a bonding terminal (power supply terminal), and an electrode lead-out portion. The ceramic base has an upper surface serving as a wafer placement surface. The FR attraction electrode is embedded in the ceramic base. The power supply terminal is inserted into the ceramic base from a lower surface of the ceramic base and penetrates a through-hole formed in the FR attraction electrode. The electrode lead-out portion is provided at each of two or more positions at intervals along a peripheral edge of the through-hole to be thicker than the FR attraction electrode and has an inner peripheral surface bonded to a side surface of the power supply terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.