Semiconductor package
US12300668B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 16, 2022 |
| Grant date | May 13, 2025 |
| Priority date | — |
| Expiry date | Nov 14, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06562
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package comprising a substrate including substrate pads on a top surface thereof, a first upper semiconductor chip on the substrate and including conductive chip pads, and bonding wires coupled to the substrate pads and the first upper semiconductor chip. The bonding wires include first and second bonding wires. The substrate has a first region between the conductive chip pads and the substrate pads, and a second region between the first region and the substrate pads. The second bonding wire has a maximum vertical level on the first region of the substrate. On the first region of the substrate, the first bonding wire is at a level higher than that of the second bonding wire. On the second region of the substrate, the second bonding wire is at a level higher than that of the first bonding wire.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.