Array substrate and display panel
US12300701B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 2021 |
| Grant date | May 13, 2025 |
| Priority date | — |
| Expiry date | Dec 9, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/441
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An array substrate and a display panel are provided. The array substrate includes a substrate, an array layer, an inorganic insulation layer, a conductive electrode, a passivation layer, and a pixel electrode disposed in sequence. The array layer includes a source electrode and a drain electrode. A first via hole is defined in the array substrate. The first via hole penetrates the passivation layer and the inorganic insulation layer and exposes the drain electrode. The pixel electrode is connected to the drain electrode in the first via hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.