Semiconductor structure and manufacturing method thereof

US12300744B2 · kind B2 · utility

Assignee

• CHANGXIN MEMORY TECHNOLOGIES, INC. · CN

Inventors

• Deyuan Xiao · Shanghai, CN
• Guangsu SHAO · Hefei, CN
• Yunsong QIU · Hefei, CN
• Yi Jiang · Hefei, CN
• Youming Liu · Longbeilingcun, CN

Key dates

• Filing date: Sep 26, 2022
• Grant date: May 13, 2025
• Expiry date: Nov 18, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/252

Abstract

The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a base, including a semiconductor substrate, the semiconductor substrate is provided with first trenches extending along a first direction and second trenches extending along a second direction, the first trenches intersect with the second trenches to form a plurality of semiconductor pillars on the semiconductor substrate, the second trench is filled with a first dielectric layer, a second dielectric layer is provided on a top of the semiconductor pillar, and a third dielectric layer is provided on a sidewall of the first trench; an isolation layer, located in the semiconductor substrate below the first trenches and extending along the second direction; and a bit line, located on a surface of the isolation layer and extending along the second direction, the bit line is connected to a bottom of the semiconductor pillar.