Systems and methods for tuning capacitance in quantum devices
US12301225B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 21, 2022 |
| Grant date | May 13, 2025 |
| Priority date | — |
| Expiry date | Jul 21, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N60/12
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
Systems and methods for capacitance tuning of devices in quantum processors are described. One implementation is a quantum processor with a first current path having a first loop, a Josephson structure with at least one Josephson junction interrupting the first loop, a second current path connected to the first current path, and a flux bias. The second current path has a first node spaced from a second node, a capacitor separating the first node and the second node, and a voltage gain tuner, the voltage gain tuner being inductively coupled to the inductance of the first current path. The flux bias is coupled to the voltage gain tuner and controls the voltage gain tuner to vary a voltage ratio between the first node and the second node, thereby influencing the capacitance of the first current path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.