Ultra low latency pattern matching system and method
US12301233B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 6, 2024 |
| Grant date | May 13, 2025 |
| Priority date | — |
| Expiry date | Aug 6, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17708
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In one or more implementations, a data processing device and a data processing method are disclosed that includes a data communication port configured to transmit and receive data to and from at least one computing device. Further, a replicator is included that is configured to replicate ingress data received from the data communication port to a pattern matcher and a field programmable gate array. The pattern matcher is configured to receive the replicated data directly from the replicator and to generate and transmit a trigger signal to the field programmable gate array. Still further, the field programmable gate array is configured to receive the replicated data from the replicator and the trigger signal from the pattern matcher and to perform bit operations on the replicated data as a function of the trigger signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.