Three-dimensional semiconductor memory devices, methods of fabricating the same, and electronic systems including the same
US12302563B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2021 |
| Grant date | May 13, 2025 |
| Priority date | — |
| Expiry date | Jul 28, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
Abstract
Disclosed are three-dimensional semiconductor memory devices, electronic systems including the same, and methods of fabricating the same. The three-dimensional semiconductor memory device includes a substrate including a cell array region and an extension region, a peripheral circuit structure including peripheral transistors on the substrate, a stack structure including interlayer dielectric layers and gate electrodes that are alternately stacked on the peripheral circuit structure, contacts that penetrate the stack structure on the extension region and are electrically connected with the peripheral transistors and include a protruding part contacting a sidewall of one of the gate electrodes and a vertical part penetrating the stack structure, and dielectric patterns between the vertical part and respective sidewalls of the gate electrodes. Top and bottom surfaces of each of the dielectric patterns are respectively in contact with adjacent ones of the interlayer dielectric layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.