Semiconductor device and preparation method thereof
US12302622B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 31, 2022 |
| Grant date | May 13, 2025 |
| Priority date | — |
| Expiry date | Aug 16, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8503
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed are a semiconductor device and a preparation method thereof. The semiconductor device includes a substrate, a multilayer semiconductor layer, a dielectric layer, a source and a drain. A gate trench is formed in the multilayer semiconductor layer and the dielectric layer. A gate is formed in the gate trench, and the gate trench includes a first sub-portion of the gate trench formed in the multilayer semiconductor layer and a second sub-portion of the gate trench penetrating the dielectric layer. The second sub-portion of the gate trench includes a second opening located on the surface of the dielectric layer close to the substrate and a third opening on the surface of the dielectric layer away from the substrate. The vertical projection of the third opening on the substrate covers the vertical projection of the second opening on the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.