Integrated chip with solid-state power storage device
US12302628B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Jan 7, 2022 |
| Grant date | May 13, 2025 |
| Priority date | — |
| Expiry date | Mar 3, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/522
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to an integrated chip including a first metal layer over a substrate. A second metal layer is over the first metal layer. An ionic crystal layer is between the first metal layer and the second metal layer. A metal oxide layer is between the first metal layer and the second metal layer. The first metal layer, the second metal layer, the ionic crystal layer, and the metal oxide layer are over a transistor device that is arranged along the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.