Array substrate and display panel
US12306509B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2023 |
| Grant date | May 20, 2025 |
| Priority date | — |
| Expiry date | Jan 10, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An array substrate and a display panel. The array substrate includes: a base substrate; a gate line and a data line on the base substrate, the gate line intersect the data line to define a pixel region; a metal oxide thin film transistor is arranged in the pixel region, the metal oxide thin film transistor includes a metal oxide semiconductor layer; the metal oxide semiconductor layer includes a first part and a second part; the first part and the data line are connected through a first via hole; the first part is in a stripe shape; a first included angle is between extension directions of the first part and the data line; an orthographic projection of the second part overlap with an orthographic projection of the gate line on the base substrate and do not overlap with an orthographic projection of the data line on the base substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.