System on a chip (SoC) having a low power mode of operation
US12306652B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 11, 2023 |
| Grant date | May 20, 2025 |
| Priority date | — |
| Expiry date | Oct 11, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/20
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In an integrated circuit, a first always on (AON) domain generates an isolation signal to enter standby mode. A switchable power domain propagates the isolation signal. A voltage level detector outputs an indicator which indicates whether a voltage of the switchable power supply is above or below a voltage threshold. An isolation wrapper circuit includes a pass-through latch selectively enabled based on the output of the voltage level detector. The pass-through latch receives the propagated isolation signal and provides a value of the propagated isolation signal at its output while enabled, but maintains a latched value at its output, regardless of changes in value of the propagated isolation signal, while disabled. The wrapper circuit also includes an isolation circuit which receives signals from circuitry within the switchable power domain and selectively isolates the received signals from a second AON power domain based on the output of the pass-through latch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.