Techniques to power balance multiple chips
US12306691B2 · kind B2 · utility
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3References
33Claims
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Inventors
Key dates
| Filing date | Oct 12, 2020 |
| Grant date | May 20, 2025 |
| Priority date | — |
| Expiry date | Sep 3, 2041 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatuses, systems, and techniques to power balance multiple chips. In at least one embodiment, a system includes a plurality of processors having substantially equal performance capability and different power consumption capability, where a cumulative power consumption of the processors is not to exceed a system power threshold if each processor is operated at substantially peak performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.