Integrated circuit providing increased pin access points and method of designing the same
US12307185B2 · kind B2 · utility
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12References
20Claims
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Key dates
| Filing date | Feb 11, 2022 |
| Grant date | May 20, 2025 |
| Priority date | — |
| Expiry date | Nov 2, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a first cell including a first lower pattern extending in a first direction along a first track in a first wiring layer; and a second cell including a second lower pattern that extends in the first direction along the first track in the first wiring layer, and is a minimum space of the first wiring layer or farther apart from the first lower pattern, wherein the first lower pattern corresponds to a pin of the first cell, and the second lower pattern is farther apart from a boundary between the first cell and the second cell than the first lower pattern is.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.