Gate on array (GOA) circuit for display panel solving problem of inconsistent impedances and capacitive reactance of clock signal carriers
US12307996B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 3, 2020 |
| Grant date | May 20, 2025 |
| Priority date | — |
| Expiry date | Nov 6, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2300/0426
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A display panel of the present application is disclosed. The display panel includes a GOA circuit, a plurality of clock main lines on a side of the GOA circuit, and a plurality of clock branch lines connected to each of the corresponding clock main lines, respectively. By providing the different first protrusion components and second protrusion components in the corresponding clock branch lines, the equivalent impedance of these clock branch lines can be adjusted to be equal. By providing the bridge components with different areas in the corresponding clock branch lines, the equivalent capacitive reactance of these clock branch lines can be adjusted to be equal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.