Anti-fuse storage layout and circuit thereof, and anti-fuse memory and design method thereof
US12308316B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 2, 2022 |
| Grant date | May 20, 2025 |
| Priority date | — |
| Expiry date | Jan 24, 2044 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments provide an anti-fuse storage layout and a circuit thereof, and an anti-fuse memory and a design method thereof. The anti-fuse storage layout includes: active regions extending along a first direction and being discretely arranged along a second direction, each of the active regions including at least two memory cell regions arranged along the first direction, each of the at least two memory cell regions including an anti-fuse region and a control region arranged along the first direction, and the control regions of the adjacent memory cell regions being adjacent to each other along the first direction; a word line region extending along the second direction and intersecting with the control region; an electrical connection region extending along the second direction and intersecting with the anti-fuse region; and a programming control region extending along a third direction and being positioned at one side of the corresponding active region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.