Multiple-reference-embedded comparator and comparison method thereof
US12308843B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 16, 2023 |
| Grant date | May 20, 2025 |
| Priority date | — |
| Expiry date | Oct 19, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/2481
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A multiple-reference-embedded comparator (MREC) circuit includes a tail current source circuit; an input transistor pair, coupled to the tail current source circuit, configured to receive differential input voltages and perform a first pre-amplification to generate first differential amplified voltages according to the differential input voltages; and a plurality of embedded reference (ER) branches, each coupled to the input transistor pair, each configured to perform a second pre-amplification to generate second differential amplified voltages according to the first differential amplified voltages, and to perform a discrete-time comparison to generate differential output voltages according to the second differential amplified voltages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.