Dual loop charge pump for enhanced reliability and power consumption
US12308847B2 · kind B2 · utility
0Cited by
9References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2023 |
| Grant date | May 20, 2025 |
| Priority date | — |
| Expiry date | Sep 22, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/099
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure provide an enhanced phase-locked loop (PLL) circuit and an enhanced charge pump circuit used for various applications, including high-speed data clock generation for complex integrated circuit (IC) designs. The disclosed PLL circuit and charge pump circuit enable significant power and supply current reduction, improved circuit reliability; reduced self-heating and electro-migration risk, and enable use of lower power operational amplifiers with the operational amplifiers driving high impedance nodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.