Frequency synthesis using a frequency dividing circuit
US12308849B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Jun 30, 2023 |
| Grant date | May 20, 2025 |
| Priority date | — |
| Expiry date | Jun 30, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0992
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In various embodiments, a frequency dividing circuit is provided. The frequency dividing circuit may include a first circuit including an m-bit multiplexer configured to receive a positive binary word and a negative binary word as inputs. The frequency dividing circuit may receive a controlled oscillator output signal and a complement of the controlled oscillator output signal, generate a frequency dividing circuit output signal from the controlled oscillator output signal and the complement of the controlled oscillator output signal using the positive binary word and the negative binary word. A ratio of the frequency dividing circuit output signal frequency to the controlled oscillator output signal frequency is a decimal value greater than zero and less than one and is determined using a ratio of a value of the positive binary word to a sum of the value of the positive binary word and an absolute value of the negative binary word.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.