Hardware queue scheduling for multi-core computing environments

US12309067B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Niall D. McDonnell · Limerick, IE
• Gage Eads · Austin, US
• Mrittika Ganguli · Tempe, US
• Chetan Hiremath · Portland, US
• John Mangan · Fairfax, US
• Stephen T. Palermo · Chandler, US
• Bruce Richardson · Ottawa, CA
• Edwin Verplanke · Chandler, US
• Praveen Mosur · Folsom, US
• Bradley Chaddick · Portland, US
• Abhishek Khade · Chandler, US
• Abhirupa Layek · Chandler, US
• Sarita Maini · Santa Clara, US
• Rahul R. Shah · Marlborough, US
• Shrikant M. Shah · Chandler, US
• William Burroughs · Macungie, US
• David P. Sonnier · Austin, US

Key dates

• Filing date: Sep 11, 2020
• Grant date: May 20, 2025
• Expiry date: Aug 23, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H04L47/6275
• WIPO field: Digital communication
• WIPO sector: Electrical engineering

Abstract

Methods, apparatus, systems, and articles of manufacture are disclosed for hardware queue scheduling for multi-core computing environments. An example apparatus includes a first core and a second core of a processor, and circuitry in a die of the processor, at least one of the first core or the second core included in the die, the at least one of the first core or the second core separate from the circuitry, the circuitry to enqueue an identifier to a queue implemented with the circuitry, the identifier associated with a data packet, assign the identifier in the queue to a first core of the processor, and in response to an execution of an operation on the data packet with the first core, provide the identifier to the second core to cause the second core to distribute the data packet.