Semiconductor structure and manufacturing method thereof
US12309999B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 1, 2022 |
| Grant date | May 20, 2025 |
| Priority date | — |
| Expiry date | Dec 14, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/488
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate; a memory cell array, located on the substrate, the memory cell array includes a plurality of transistor units, each of the transistor units includes a first transistor and a second transistor extending along a first direction and electrically connected to each other, and the first direction is parallel to the substrate; a first bit line, penetrating the memory cell array and electrically connected to the first transistor; a second bit line, penetrating the memory cell array and electrically connected to the second transistor; a first word line, electrically connected to the first transistor; and a second word line, electrically connected to the second transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.