Semiconductor structure and manufacturing method thereof
US12310030B2 · kind B2 · utility
0Cited by
5References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2022 |
| Grant date | May 20, 2025 |
| Priority date | — |
| Expiry date | Jun 22, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/01
Abstract
The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a plurality of memory cells alternately arranged on a substrate, the memory cell including an odd number of vertical transistors, a connection pad connected to one end of each of the odd number of vertical transistors, and a magnetic tunnel junction located on the connection pad; wherein a material of a channel of the vertical transistor includes a monocrystalline semiconductor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.