Method of fabricating a semiconductor device
US12310043B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 11, 2021 |
| Grant date | May 20, 2025 |
| Priority date | — |
| Expiry date | Nov 16, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0158
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a semiconductor device comprises forming a gate electrode structure over a first region of a semiconductor substrate, and forming a source/drain region on a second region of the semiconductor substrate. The gate electrode structure comprises a metal gate electrode layer, a gate dielectric layer, and gate sidewalls. The second region of the semiconductor substrate is on an opposing side of the metal gate electrode layer. The method for fabricating a semiconductor device further comprises forming an interlayer dielectric layer over the source/drain regions and the gate sidewall, and forming an oxide layer over the source/drain region and the gate sidewall without substantially forming the second oxide layer on the gate electrode layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.