Super-junction VDMOS device with low on-resistance
US12310053B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 11, 2022 |
| Grant date | May 20, 2025 |
| Priority date | — |
| Expiry date | Nov 14, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8503
Abstract
A super-junction VDMOS device with a low on-resistance includes: a super-junction structure disposed on a drain region; a super-junction structure having a first semiconductor pillar and a second semiconductor pillar. A HEMT structure having heterojunctions is formed between the first semiconductor pillar and the second semiconductor pillar. The HEMT structure includes a first semiconductor material pillar and a second semiconductor material pillar. Heterojunctions are formed in the super-junction structure to form the HEMT structure, inducing two-dimensional electronic gas to facilitate electrical conduction, such that the on-resistance of the VDMOS device is significantly reduced. The voltage difference between the first semiconductor pillar and the second semiconductor pillar in the super-junction structure is utilized to control a cutting-off behavior of the HEMT structure. The two-dimensional electronic gas is depleted when a high drain-source voltage difference is applied between the source region and the drain region, rendering the VDMOS device high-voltage resistant.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.