Integrated circuit devices including stacked transistors and methods of forming the same
US12310062B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 12, 2022 |
| Grant date | May 20, 2025 |
| Priority date | — |
| Expiry date | Sep 2, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
Integrated circuit devices may include a stacked structure including an upper transistor on a substrate and a lower transistor between the substrate and the upper transistor. The upper transistor may include an upper gate electrode, an upper active region in the upper gate electrode, and an upper gate insulator between the upper gate electrode and the upper active region. The upper active region may include an inner layer including a first semiconductor material and an outer layer that extends between the inner layer and the upper gate insulator and includes a second semiconductor material that is different from the first semiconductor material. The lower transistor may include a lower gate electrode, a lower active region in the lower gate electrode, and a lower gate insulator between the lower gate electrode and the lower active region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.