Semiconductor devices including gate spacer
US12310079B2 · kind B2 · utility
0Cited by
52References
19Claims
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Key dates
| Filing date | Oct 9, 2023 |
| Grant date | May 20, 2025 |
| Priority date | — |
| Expiry date | Oct 9, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A semiconductor device includes a first active region defined on a substrate, a first gate electrode across the first active region, a first drain region in the first active region at a position adjacent to the first gate electrode, an undercut region between the first active region and the first gate electrode, and a first gate spacer on a side surface of the first gate electrode and extending into the undercut region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.