Laterally-gated transistors and lateral Schottky diodes with integrated lateral field plate structures
US12310080B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 19, 2024 |
| Grant date | May 20, 2025 |
| Priority date | — |
| Expiry date | Mar 19, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8503
Abstract
Laterally-gated transistors and lateral Schottky diodes are disclosed. The FET includes a substrate, source and drain electrodes, channel, a gate electrode structure, and a dielectric layer. The gate electrode structure includes an electrode in contact with the channel and a lateral field plate adjacent to the electrode. The dielectric layer is disposed between the lateral field plate and the channel. The lateral field plate contacts the dielectric layer and to modulate an electric field proximal to the gate electrode proximal to the drain or source electrodes. Also disclosed is a gate electrode structure with lateral field plates symmetrically disposed relative to the gate electrode. Also disclosed in a substrate with dielectric structures buried in the substrate remote from the gate electrode structure. A lateral Schottky diode having an anode structure includes an anode (A), cathodes (C) and lateral field plates located between the anode and the cathodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.