Semiconductor strain gage
US12313479B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2024 |
| Grant date | May 27, 2025 |
| Priority date | — |
| Expiry date | Jan 10, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01L1/205
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Strain gages in accordance with the present disclosure are sculpted from a device layer of a semiconductor-on-insulator wafer using deep reactive ion etching, yielding very good control over the electrical properties and physical dimensions of the strain gages. In some embodiments, groups of fully fabricated strain gages are physically connected to handling frames via sprues, which eases handling, enables automated assembly, and facilitates tracing of individual gages from the beginning of fabrication through final packaging. In some embodiments, sprues are configured to mitigate accidental separation of the gages from their frames while simultaneously easing their removal in response to specific forces applied by a handling tool.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.