Wireline transceiver with internal and external clock generation
US12314077B2 · kind B2 · utility
0Cited by
5References
15Claims
0Family size
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Key dates
| Filing date | Nov 20, 2023 |
| Grant date | May 27, 2025 |
| Priority date | — |
| Expiry date | Nov 20, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device having functional circuitry driven by a clock signal includes onboard clock generation circuitry. The clock generation circuitry includes an input configured to accept a frequency reference signal, at least one variable loading capacitor coupled to the input for converting the crystal resonator signal into a calibrated clock signal, and calibration circuitry configured to calibrate the at least one variable loading capacitor based on a reference voltage. The input configured to accept a frequency reference signal may be configured to accept a crystal resonator signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.