Patent · US Active

Systems and methods for adaptive power multiplexing

US12314116B2 · kind B2 · utility

0Cited by

5References

16Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Giby Samson · San Diego, US
Smeeta Heggond · Bagalkote, IN
Jitu Khushalbhai Mistry · San Diego, US
Paras Gupta · San Diego, US
Keyurkumar Karsanbhai Kansagra · Kanchinakote, IN
Kamesh MEDISETTI · Bengaluru, IN
Ramaprasath Vilangudipitchai · San Diego, US
Arshath Sheeparamatti · San Diego, US

Key dates

Filing date	Jul 28, 2021
Grant date	May 27, 2025
Priority date	—
Expiry date	Nov 5, 2041

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A system on chip (SOC) comprising: first memory block and a second memory block; a processing unit coupled to the first memory block and the second memory block; a first power multiplexor disposed between the first memory block and the second memory block and coupled to a first power rail configured to provide an operating voltage to both the first memory block and the second memory block; and enable logic circuitry disposed at a periphery of the SOC away from the first memory block and the second memory block, the enable logic being coupled to control terminals of the first power multiplexor.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.