PCIe fault auto-repair method, apparatus and device, and readable storage medium
US12314127B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 28, 2022 |
| Grant date | May 27, 2025 |
| Priority date | — |
| Expiry date | Apr 28, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/81
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Peripheral Component Interconnect express (PCIe) fault auto-repair method is provided. According to the method, when a PCIe link in a system runs, an operation state of the system is monitored by acquiring a Correctable Error (CE) error count and an Uncorrectable Error (UCE) error count in the PCIe link; when the CE error count reaches a corresponding error threshold value, or the UCE error count reaches a corresponding error threshold value, an error device is removed from the system to avoid continuous adverse influence of the error device on operation of the system. Moreover, an SI parameter register of the error device is modified according to pre-stored optimization parameters of all PCIe devices in a server, the SI parameter of the error device is automatically optimized, and the error device is re-accessed to the system after the PCIe fault repair.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.