Cache memory with per-sector cache residency controls
US12314175B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 23, 2022 |
| Grant date | May 27, 2025 |
| Priority date | — |
| Expiry date | Apr 7, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/60
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various embodiments include techniques for managing cache memory in a computing system. The computing system includes a sectored cache memory that provides a mechanism for software applications to directly invalidate data items stored in the cache memory on a sector-by-sector basis, where a sector is smaller than a cache line. When all sectors in a cache line have been invalidated, the cache line is implicitly invalidated, freeing the cache line to be reallocated for other purposes. In cases where the data items to be invalidated can be aligned to sector boundaries, the disclosed techniques effectively use status indicators in the cache tag memory to track which sectors, and corresponding data items, have been invalidated by the software application. Thus, the disclosed techniques thereby enable a low-overhead solution for invalidating individual data items that are smaller than a cache line without additional tracking data structures or consuming additional memory transfer bandwidth.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.