Memory with extension mode
US12314586B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2023 |
| Grant date | May 27, 2025 |
| Priority date | — |
| Expiry date | Dec 20, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes a main memory, an auxiliary memory, a redundancy circuit, an extension control terminal, and a multiplexer. The main memory has a line width, and includes a write data input. The auxiliary memory has the same line width as the main memory, and includes a write data input. The redundancy circuit includes and input and an output. The input is coupled to the write data input of the main memory. The multiplexer includes a first input, a second input, a control input, and an output. The first input is coupled to the write data input of the main memory. The second input is coupled to the output of the redundancy circuit. The control input is coupled to the extension control terminal. The output of the multiplexer is coupled to the write data input of the auxiliary memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.