Decoding drive circuit and method therefor, word line decoding circuit and semiconductor memory
US12315554B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 8, 2023 |
| Grant date | May 27, 2025 |
| Priority date | — |
| Expiry date | Aug 25, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A decoding drive circuit includes at least one decoding driver. The decoding driver includes a first-stage drive circuit and a second-stage drive circuit. Herein, the first-stage drive circuit is configured to receive an enabling control signal, a decoding input signal and a drive control signal, and generate a first drive signal and a second drive signal according to the enabling control signal, the drive control signal and the decoding input signal. The second-stage drive circuit is configured to generate a target word line drive signal according to the first drive signal and the second drive signal. Thus, the embodiments of the disclosure provide a new decoding drive circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.