Memory and method of operation with dummy and loaded route
US12315557B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 14, 2023 |
| Grant date | May 27, 2025 |
| Priority date | — |
| Expiry date | Aug 26, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4093
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory includes: a storage cell array; a write driver; and a first column decoder, the first column selection line includes a dummy route and a loaded route, the dummy route is coupled to the first column decoder and the loaded route and transmits a first column selection signal to the loaded route; the loaded route is coupled to a first storage cell area and transmits the first column selection signal to the first storage cell area; the first column selection signal selects a storage cell column, on which a write operation is performed, from the first storage cell area. A transmission direction of a data signal to be written transmitted by the write driver is identical to a transmission direction of the first column selection signal transmitted via the loaded route.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.