Memory device configured to reduce verification time and operating method thereof including dump operations
US12315590B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 12, 2022 |
| Grant date | May 27, 2025 |
| Priority date | — |
| Expiry date | Jul 11, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a memory cell array having memory cells therein that are programed to a plurality of program states, and a page buffer circuit having a plurality of page buffers therein that are connected to a plurality of bit lines associated with the memory cell array. Each of the page buffers includes a sensing latch that is connected to a corresponding one of the plurality of bit lines, and is configured to control a precharge operation performed on a corresponding bit line. Control logic is provided to control a verification operation performed on the plurality of program states within the memory cells by controlling the page buffer circuit, a plurality of dump operations on the sensing latch, which are based on values of at least two bits stored in each of the page buffers, and a selective precharge of bit lines that are connected to memory cells to be programmed to a first program state to be verified, from among the plurality of program states.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.