Write leveling circuit applied to memory, and method and apparatus for controlling the same
US12315595B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Aug 16, 2023 |
| Grant date | May 27, 2025 |
| Priority date | — |
| Expiry date | Feb 21, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A write leveling circuit applied to a memory includes: a write signal generation circuit configured to perform delay processing on a first write signal according to a received first clock signal, and output a second write signal; a delay circuit configured to perform delay processing on a received first data strobe signal, and output a second data strobe signal; and a sampling circuit connected to both the delay circuit and the write signal generation circuit, and configured to output a first sampling signal according to the received second data strobe signal and the received second write signal. The sampling circuit is further configured to receive the first data strobe signal, and output a second sampling signal according to the first data strobe signal and the second write signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.