Word line driver, word line driver array, and semiconductor structure
US12315596B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 12, 2023 |
| Grant date | May 27, 2025 |
| Priority date | — |
| Expiry date | Jul 14, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure provide a word line driver, a word line driver array, and a semiconductor structure, relating to the technical field of semiconductors. The word line driver includes: a zeroth P-channel metal oxide semiconductor (PMOS) transistor, a zeroth N-channel metal oxide semiconductor (NMOS) transistor, and a first NMOS transistor, the zeroth PMOS transistor being provided with a gate connected to a gate of the first NMOS transistor and configured to receive a first control signal, a source configured to receive a second control signal, and a drain connected to a drain of the first NMOS transistor, the zeroth NMOS transistor being provided with a gate configured to receive a second control complementary signal, and a drain of the zeroth NMOS transistor and the drain of the first NMOS transistor being configured to be connected to a word line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.