Method of manufacturing electronic device with reduced substrate warpage
US12315741B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2022 |
| Grant date | May 27, 2025 |
| Priority date | — |
| Expiry date | Jul 14, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/81815
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing an electronic device includes providing a substrate, providing an intermediate layer on the substrate, and providing an isolation layer on the intermediate layer. The substrate includes an active region and a peripheral region. The peripheral region is adjacent to the active region, and the ratio of the area of the active region to the area of the substrate surface is between 75% and 92%. The isolation layer includes a first surface and at least one slope. The first surface of the isolation layer is correspondingly disposed in the active region. The at least one slope of the isolation layer is correspondingly disposed in the peripheral region and at a first angle with respect to the substrate surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.