Automatic calibration of a ring phase locked loop
US12316335B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2023 |
| Grant date | May 27, 2025 |
| Priority date | — |
| Expiry date | Jul 30, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system for automatically calibrating a phase locked loop (PLL), the system comprising: a node a voltage controlled oscillator (VCO) coupled to the node and configured to provide an output signal to the node; at least one digital-to-analog converter (DAC) coupled to the VCO and configured to provide a voltage to the VCO; and at least one controller configured to: determine an output frequency of the output signal; responsive to determining the output frequency, compare the output frequency to the voltage; responsive to determining the output frequency, compare the output frequency to a target frequency; and control the DAC to modify the voltage based on a comparison of the output frequency to the voltage and a comparison of the output frequency to the target frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.