Hardware circuit to perform round computations of ARX-based stream ciphers
US12316742B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2017 |
| Grant date | May 27, 2025 |
| Priority date | — |
| Expiry date | Oct 21, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L9/0861
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Systems and methods for efficient computation of stream ciphers. An example system for implementing a stream cipher, may comprise: a sub-round computation circuit of a first type configured to perform a subset of transformations of a cipher computation round on a round input state, each transformation of the subset of transformations including at least one of: a bitwise addition operation, a bitwise exclusive disjunction operation, or a bitwise rotation operation. The sub-round computation circuit of the first type may comprise: one or more of sub-round computation circuits of a second type, wherein each sub-round computation circuit of the second type is configured to perform the subset of transformations of the cipher computation round on a respective part of the round input state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.