Semiconductor memory device
US12317507B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 2022 |
| Grant date | May 27, 2025 |
| Priority date | — |
| Expiry date | Dec 13, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B51/40
Abstract
Disclosed is a semiconductor memory device including a substrate, a plurality of source lines extending in a first direction on the substrate, a plurality of word lines crossing the source lines and extending in a second direction different from the first direction, a plurality of bit lines crossing the source lines and the word lines and extending in a third direction different from the first direction and the second direction, and a plurality of memory cells disposed at intersections between the source lines, the word lines, and the bit lines. The first, second, and third directions are parallel to a top surface of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.