Patent · US Active

Contaminant collection on SOI

US12317519B2 · kind B2 · utility

0Cited by

1References

24Claims

0Family size

Assignee

TEXAS INSTRUMENTS INCORPORATED · US

Inventors

Honglin Guo · Plano, US
Zachary K. Lee · Fremont, US
Jingjing Chen · Fuzhou, CN

Key dates

Filing date	Jan 9, 2024
Grant date	May 27, 2025
Priority date	—
Expiry date	Jan 9, 2044

Classification

Technology area (CPC H)Electricity
CPC primaryH10D64/01
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

An integrated circuit includes an SOI substrate having a semiconductor layer over a buried insulator layer; the semiconductor layer contains white space regions that include a PWELL region. An electronic device includes an NWELL region in the semiconductor layer, a dielectric over the NWELL region, and a polysilicon plate over the dielectric. A sacrificial NWELL ring is adjacent to and separated from the NWELL region by a first gap.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.