Semiconductor device and manufacturing method thereof
US12317530B2 · kind B2 · utility
0Cited by
9References
20Claims
0Family size
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Key dates
| Filing date | Jul 31, 2023 |
| Grant date | May 27, 2025 |
| Priority date | — |
| Expiry date | Jul 31, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/307
Abstract
A semiconductor device includes a doped region of a first conductivity type in a substrate, a source/drain region of the first conductivity in the doped region, and a gate structure overlapping a portion of the doped region. The semiconductor device further comprises a multi-layer spacer over a first sidewall of the gate structure. The multi-layer spacer comprises a first spacer layer, a second spacer layer over the first spacer layer, and a third spacer layer over the second spacer layer. The first spacer layer and the second spacer layer are in contact with the first sidewall of the gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.