Process for protecting an upper stage of electronic components of an integrated circuit against antenna effects
US12317603B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 23, 2022 |
| Grant date | May 27, 2025 |
| Priority date | — |
| Expiry date | Apr 26, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06541
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for protecting an upper stage of an electronic components against antenna effects includes providing a first structure having a first substrate with a first surface, a first stage of electronic components formed in a second surface of the first substrate, and a first stack having a last metallization level electrically connected to the second surface; and providing a second structure having a second substrate with a through-substrate via and having a second stage of electronic components having protective components that are arranged to drain electric charges to the second substrate. The process also includes joining the first and second structures so that the through-substrate via is electrically connected to the last metallization level of the first stack and forming a second stack on the second stage having a first metallization level electrically connected to the through-substrate via and to the first surface of the second substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.