Array substrate with overlapping active layers having channel width greater than gate width, method for preparing the same, and display panel
US12317684B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2024 |
| Grant date | May 27, 2025 |
| Priority date | — |
| Expiry date | Jun 18, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
Abstract
The present application relates to the technical field of display panels, and provides an array substrate and a method for preparing the same, and a display panel. The array substrate includes a base substrate, a buffer layer, an active layer, a gate insulation layer, a first gate, an interlayer insulation layer, a source and a drain that are laminated. The active layer includes the first active layer and the two second active layers, and the first active layer forms the channel region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.