Dynamic voltage frequency scaling to reduce test time
US12320850B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 12, 2023 |
| Grant date | Jun 3, 2025 |
| Priority date | — |
| Expiry date | Sep 12, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318575
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus is used for performing a scan test on a chip. In certain configurations, the apparatus includes an internal voltage source on a same die of the chip. The internal voltage source receives a constant voltage. The internal voltage source generates an internal voltage based on the constant voltage. The internal voltage is maintained at a lower voltage level in a capture phase of the scan test, and is increased from the lower voltage level to a high voltage level at a start of a shift phase of the scan test and reduced from the high voltage level to the lower voltage level at an end of the shift phase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.