Multiple and cascaded redundant disciplined oscillator systems in a spoofing resistant reference time source system and methods thereof
US12320903B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2022 |
| Grant date | Jun 3, 2025 |
| Priority date | — |
| Expiry date | Dec 8, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0688
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system, non-transitory computer readable medium, and method include entering redundant oscillators and a cascaded oscillator of a spoofing resistant system into an initialization state. All but one of the redundant oscillators are disciplined to a time-and-frequency external input into normal disciplining state with the remaining one of the redundant oscillators in a holdover state. When all but one of the redundant oscillators have reached the normal disciplining state, placing all but one of the redundant oscillators into the holdover state, disciplining the remaining one of the redundant oscillators to the time and frequency external input, and disciplining the cascaded oscillator to one of the all but one of the redundant oscillators now in the holdover state. When the remaining one of the redundant oscillators and the cascaded oscillator have reached the normal disciplining state, transitioning from an initialization stage to a steady state management stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.